1. Field of the Invention
The present invention relates to a structure of an element provided with a gate electrode and a source/drain region, which are required for miniaturization, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a semiconductor device is required for miniaturization more and more. Particularly a shallower junction is demanded in MISFET (Metal Insulated Semiconductor Field Effect Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, there are limits of formation of the shallow junction in the conventional method as the miniaturization is proceeding. The conventional method of manufacturing a MISFET will be described below referring to FIGS. 21A to 21D. FIGS. 21A to 21D are sectional views of the method of manufacturing a MISFET having the conventional structure.
As shown in FIG. 21A, an element isolation region 102 is formed in a semiconductor substrate 101 made of silicon using STI (Shallow Trench Isolation) technology or the like. The semiconductor substrate 101 is, e.g. an n-type semiconductor. Then, gate formation is carried out in such a manner that, e.g. a gate nitride-oxide film having a thickness of about 1 nm is formed as a gate insulating film 103 and a polysilicon film 104 having the thickness of 100 nm is formed as a gate electrode 104. A p-type extension region 105, which is the shallow portion of the source/drain region, is formed using ion implantation technology. A thermal process after the ion implantation is carried out to the extent to which a crystal broken by the ion implantation is recovered. Specifically it is sufficient to carry out RTA (Rapid Thermal Annealing) at 800° C. for several seconds.
As shown in FIG. 21B, using deposition of a silicon nitride film, a silicon oxide film, or the like and etching, a gate side-wall insulator 106 is formed on a side face of the gate electrode 104, and a contact junction region 107 which is a deep junction portion of the source/drain is formed. The same impurity for the contact junction region 107 is also doped into the gate electrode 104 by the ion implantation into the contact junction region 107.
As shown in FIG. 21C, in order to activate the ion doped into the contact junction region 107 and the gate electrode 104, an activation process is carried out at a temperature not lower than 1000° C. That such a high temperature is required is because depletion of the gate is suppressed. This heat treatment forms an extension region 108 which is deeper than the extension region 105.
As shown in FIG. 21D, using silicide technology, a silicide layer 109 made of Co, Ni, or the like is formed on a surface of the contact junction region 107 and a top surface of the gate electrode 104, on which silicon is exposed.
The MOSFET element referred usually to as silicide gate is completed by the above-described process. The conventional method of manufacturing the MISFET and its problem will be described below referring to FIGS. 22 to 25. FIG. 22 is a concentration distribution of As in a depth direction of a silicon wafer which the ion implantation of As (arsenic) has been carried out in an extremely shallow portion, and FIG. 23 is a concentra-tion distribution of B in the depth direction of the silicon wafer which the ion implantation of B (boron) has been carried out in the extremely shallow portion. FIGS. 24A and 24B are enlarged views showing an edge of the gate electrode of the semiconductor substrate in which the MISFET is formed. FIG. 25 is a sectional view of the MISFET in which the extension regions are connected between the source region and the drain region.
One of the problems concerning the miniaturization of the MOSFET is that the extension region 105, which is the shallow junction, is deepened by the heat treatment not lower than 1000° C. FIGS. 22 and 23 are the concentration distributions of As and B in the depth direction of the silicon wafer which the ion implantation of As and B have been carried out in the extremely shallow portion, respectively. In these cases, the concentration distribution is compared before and after the heat treatment at 1085° C. As can be seen from FIGS. 22 and 23, in the case that only the heat treatment at 800° C. for several seconds is carried out, even if the current ion implantation technology is adopted, it is found that the junction of about 10 nm is formed. Junction depth is a position where the concentration of As or B becomes equal to channel concentration. The channel concentration is the region where the concentration is in the range from about 1×1018/cm3 to about 1×1019/cm3 in the case that gate length is not more than 50 nm. However, in the case of the heat treatment at 1085° C., it is found that the junction depth of boron becomes about 30 nm.
FIGS. 24A and 24B are the enlarged views showing the edge of the gate electrode of the semiconductor substrate in which the MOSFET is formed. FIGS. 24A and 24B show states of the extension region 105 before the heat treatment not lower than 1000° C. and the extension region 108 which has been deepened after the heat treatment. The extension region 108 also extends in a lateral direction at the same time the extension region 108 is deepened after the heat treatment. That the extension region 108 extends in the lateral direction is because a high concentration region 110 not lower than 1×1019/cm3 becomes a diffusion source. Usually the amount of lateral extension is about two-third in the depth (A) direction (A×2/3). Estimating the amount of extension from FIG. 22, it is found that the extension region laterally extends not lower than 20 nm as shown in FIG. 24B. Therefore, as shown in FIG. 25, when the gate length becomes not more than 40 nm, the extension regions are connected between the source and the drain and operation of the MOSFET can no longer be realized.
Thus, in order to prevent the extension regions from connecting, there is known a technology which cuts off the connection of the extension regions by ion-implanting a reversely conductive type impurity into the extension region (for example, a p-type impurity is ion-implanted in the case that the extension region is the n-type) to decrease substantially impurity concentration and by reducing the extent of the region acting as the extension region. However, this technology not only complicates the process but also results in degradation of transistor performance, so that it is an undesired method.